STM32F7 5 Reset and clock control (RCC)

  • 62 Replies
  • 829 Views
*

Offline tha

  • *****
  • 4663
    • View Profile
Re: STM32F7 5 Reset and clock control (RCC)
« Reply #32 on: September 23, 2022, 08:53:40 am »
5.3.4 RCC clock interrupt register (RCC_CIR)

Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access



Bits 31:24 Reserved, must be kept at reset value.

Bit 23 CSSC: Clock security system interrupt clear
     บิตนี้ถูกเซ็ตโดย software เพื่อเคลียร์ the CSSF flag.
     0: No effect
     1: Clear CSSF flag

Bit 22 PLLSAIRDYC: PLLSAI Ready Interrupt Clear
     บิตนี้ถูกเซ็ตโดย software เพื่อเคลียร์ PLLSAIRDYF flag. มันถูกรีเซ็ตโดย hardware เมื่อ the PLLSAIRDYF ถูกเคลียร์.
     0: PLLSAIRDYF ไม่ถูกเคลียร์
     1: PLLSAIRDYF ถูกเคลียร์

Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear
     This bit is set by software to clear the PLLI2SRDYF flag.
     0: No effect
     1: PLLI2SRDYF cleared

Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
     This bit is set by software to clear the PLLRDYF flag.
     0: No effect
     1: PLLRDYF cleared

Bit 19 HSERDYC: HSE ready interrupt clear
     This bit is set by software to clear the HSERDYF flag.
     0: No effect
     1: HSERDYF cleared

Bit 18 HSIRDYC: HSI ready interrupt clear
     This bit is set software to clear the HSIRDYF flag.
     0: No effect
     1: HSIRDYF cleared

Bit 17 LSERDYC: LSE ready interrupt clear
     This bit is set by software to clear the LSERDYF flag.
     0: No effect
     1: LSERDYF cleared

Bit 16 LSIRDYC: LSI ready interrupt clear
     This bit is set by software to clear the LSIRDYF flag.
     0: No effect
     1: LSIRDYF cleared

*

Offline tha

  • *****
  • 4663
    • View Profile
Re: STM32F7 5 Reset and clock control (RCC)
« Reply #33 on: September 23, 2022, 09:21:06 am »
Bit 15 Reserved, must be kept at reset value.

Bit 14 PLLSAIRDYIE: PLLSAI Ready Interrupt Enable
     บิตนี้ถูกเซ็ตและรีเซ็ตโดย software เพื่อเปิดใช้งาน/ปิดใช้งาน interrupt ที่เกิดจาก PLLSAI lock.
     0: PLLSAI lock interrupt ถูกปิดใช้งาน
     1: PLLSAI lock interrupt ถูกเปิดใช้งาน

Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable
     This bit is set and cleared by software to enable/disable interrupt caused by PLLI2S lock.
     0: PLLI2S lock interrupt disabled
     1: PLLI2S lock interrupt enabled

Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable
     This bit is set and cleared by software to enable/disable interrupt caused by PLL lock.
     0: PLL lock interrupt disabled
     1: PLL lock interrupt enabled

Bit 11 HSERDYIE: HSE ready interrupt enable
     This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.
     0: HSE ready interrupt disabled
     1: HSE ready interrupt enabled

Bit 10 HSIRDYIE: HSI ready interrupt enable
     This bit is set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization.
     0: HSI ready interrupt disabled
     1: HSI ready interrupt enabled

Bit 9 LSERDYIE: LSE ready interrupt enable
     This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
     0: LSE ready interrupt disabled
     1: LSE ready interrupt enabled

Bit 8 LSIRDYIE: LSI ready interrupt enable
     This bit is set and cleared by software to enable/disable interrupt caused by LSI oscillator stabilization.
     0: LSI ready interrupt disabled
     1: LSI ready interrupt enabled

*

Offline tha

  • *****
  • 4663
    • View Profile
Re: STM32F7 5 Reset and clock control (RCC)
« Reply #34 on: September 23, 2022, 09:56:46 am »
Bit 7 CSSF: Clock security system interrupt flag
     บิตนี้ถูกเซ็ตโดย hardware เมื่อ a failure ถูกตรวจพบใน the HSE oscillator.
     มันถูกเคลียร์โดย software โดยการเซ็ต the CSSC bit.
     0: No clock security interrupt ที่เกิดจาก HSE clock failure
     1: Clock security interrupt ที่เกิดจาก HSE clock failure

Bit 6 PLLSAIRDYF: PLLSAI Ready Interrupt flag
     บิตนี้ถูกเซ็ตโดย hardware เมื่อ the PLLSAI ถูกล็อคและ PLLSAIRDYDIE ถูกเซ็ต.
     มันถูกเคลียร์โดย software โดยการเซ็ต the PLLSAIRDYC bit.
     0: No clock ready interrupt ที่เกิดจาก PLLSAI lock
     1: Clock ready interrupt ที่เกิดจาก PLLSAI lock

Bit 5 PLLI2SRDYF: PLLI2S ready interrupt flag
     This bit is set by hardware when the PLLI2S is locked and PLLI2SRDYDIE is set.
     It is cleared by software by setting the PLLRI2SDYC bit.
     0: No clock ready interrupt caused by PLLI2S lock
     1: Clock ready interrupt caused by PLLI2S lock

Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag
     This bit is set by hardware when PLL is locked and PLLRDYDIE is set.
     It is cleared by software setting the PLLRDYC bit.
     0: No clock ready interrupt caused by PLL lock
     1: Clock ready interrupt caused by PLL lock

Bit 3 HSERDYF: HSE ready interrupt flag
     บิตนี้ถูกเซ็ตโดย hardware เมื่อ External High Speed clock เสถียรแล้วและ HSERDYDIE ถูกเซ็ต.
     มันถูกเคลียร์โดย software โดยการเซ็ต the HSERDYC bit.
     0: No clock ready interrupt ที่เกิดจาก the HSE oscillator
     1: Clock ready interrupt ที่เกิดจาก the HSE oscillator

Bit 2 HSIRDYF: HSI ready interrupt flag
     This bit is set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set.
     It is cleared by software by setting the HSIRDYC bit.
     0: No clock ready interrupt caused by the HSI oscillator
     1: Clock ready interrupt caused by the HSI oscillator

Bit 1 LSERDYF: LSE ready interrupt flag
     This bit is set by hardware when the External low-speed clock becomes stable and LSERDYDIE is set.
     It is cleared by software by setting the LSERDYC bit.
     0: No clock ready interrupt caused by the LSE oscillator
     1: Clock ready interrupt caused by the LSE oscillator

Bit 0 LSIRDYF: LSI ready interrupt flag
     This bit is set by hardware when the internal low-speed clock becomes stable and LSIRDYDIE is set.
     It is cleared by software by setting the LSIRDYC bit.
     0: No clock ready interrupt caused by the LSI oscillator
     1: Clock ready interrupt caused by the LSI oscillator

*

Offline tha

  • *****
  • 4663
    • View Profile
Re: STM32F7 5 Reset and clock control (RCC)
« Reply #35 on: September 23, 2022, 01:46:03 pm »
5.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access



Bits 31:30 สงวนไว้, ต้องถูกเก็บไว้ที่ reset value.

Bit 29 OTGHSRST: USB OTG HS module reset
     บิตนี้ถูกเซ็ตและเคลียร์โดย software.
     0: ไม่รีเซ็ต the USB OTG HS module
     1: รีเซ็ต the USB OTG HS module

Bits 28:26 Reserved, must be kept at reset value.

Bit 25 ETHMACRST: Ethernet MAC reset
     This bit is set and cleared by software.
     0: does not reset Ethernet MAC
     1: resets Ethernet MAC

Bit 24 Reserved, must be kept at reset value.

Bit 23 DMA2DRST: DMA2D reset
     This bit is set and reset by software.
     0: does not reset DMA2D
     1: resets DMA2D

Bit 22 DMA2RST: DMA2 reset
     This bit is set and cleared by software.
     0: does not reset DMA2
     1: resets DMA2

Bit 21 DMA1RST: DMA2 reset   (เป็น DMA1 มั๊ย หนังสือเขาเขียนผิดมามั๊ย)
     This bit is set and cleared by software.
     0: does not reset DMA2
     1: resets DMA2

Bits 20:13 Reserved, must be kept at reset value.

Bit 12 CRCRST: CRC reset
     This bit is set and cleared by software.
     0: does not reset CRC
     1: resets CRC

Bit 11 Reserved, must be kept at reset value.

Bit 10 GPIOKRST: IO port K reset
     This bit is set and cleared by software.
     0: does not reset IO port K
     1: resets IO port K

Bit 9 GPIOJRST: IO port J reset
     This bit is set and cleared by software.
     0: does not reset IO port J
     1: resets IO port J

Bit 8 GPIOIRST: IO port I reset
     This bit is set and cleared by software.
     0: does not reset IO port I
     1: resets IO port I

Bit 7 GPIOHRST: IO port H reset
     This bit is set and cleared by software.
     0: does not reset IO port H
     1: resets IO port H

Bit 6 GPIOGRST: IO port G reset
     This bit is set and cleared by software.
     0: does not reset IO port G
     1: resets IO port G

Bit 5 GPIOFRST: IO port F reset
    This bit is set and cleared by software.
     0: does not reset IO port F
     1: resets IO port F

Bit 4 GPIOERST: IO port E reset
     This bit is set and cleared by software.
     0: does not reset IO port E
     1: resets IO port E

Bit 3 GPIODRST: IO port D reset
     This bit is set and cleared by software.
     0: does not reset IO port D
     1: resets IO port D

Bit 2 GPIOCRST: IO port C reset
     This bit is set and cleared by software.
     0: does not reset IO port C
     1: resets IO port C

Bit 1 GPIOBRST: IO port B reset
     This bit is set and cleared by software.
     0: does not reset IO port B
     1:resets IO port B

Bit 0 GPIOARST: IO port A reset
     This bit is set and cleared by software.
     0: does not reset IO port A
     1: resets IO port A

*

Offline tha

  • *****
  • 4663
    • View Profile
Re: STM32F7 5 Reset and clock control (RCC)
« Reply #36 on: September 23, 2022, 02:00:42 pm »
5.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)

Address offset: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access



Bits 31:8 สงวนไว้, ต้องถูกเก็บไว้ที่ reset value.

Bit 7 OTGFSRST: USB OTG FS module reset
     เซ็ตและเคลียร์โดย software.
     0: ไม่รีเซ็ต the USB OTG FS module
     1: รีเซ็ต the USB OTG FS module

Bit 6 RNGRST: Random number generator module reset
     Set and cleared by software.
     0: does not reset the random number generator module
     1: resets the random number generator module

Bit 5 HASHRST: Hash module reset
     Set and cleared by software.
     0: does not reset the HASH module
     1: resets the HASH module

Bit 4 CRYPRST: Cryptographic module reset
     Set and cleared by software.
     0: does not reset the cryptographic module
     1: resets the cryptographic module

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 DCMIRST: Camera interface reset
     Set and cleared by software.
     0: does not reset the Camera interface
     1: resets the Camera interface

*

Offline tha

  • *****
  • 4663
    • View Profile
Re: STM32F7 5 Reset and clock control (RCC)
« Reply #37 on: September 23, 2022, 02:24:40 pm »
5.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)

Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access



Bits 31:2 Reserved, must be kept at reset value.

Bit 1 QSPIRST: Quad SPI memory controller reset
     เซ็ตและเคลียร์โดย software.
     0: ไม่รีเซ็ต the QUADSPI memory controller
     1: รีเซ็ต the QUADSPI memory controller

Bit 0 FMCRST: Flexible memory controller module reset
     Set and cleared by software.
     0: does not reset the FMC module
     1: resets the FMC module

*

Offline tha

  • *****
  • 4663
    • View Profile
Re: STM32F7 5 Reset and clock control (RCC)
« Reply #38 on: September 23, 2022, 02:44:29 pm »
5.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.



Bit 31 UART8RST: UART8 reset
     เซ็ตและเคลียร์โดย software.
     0: ไม่รีเซ็ต UART8
     1: รีเซ็ต UART8

Bit 30 UART7RST: UART7 reset
     Set and cleared by software.
     0: does not reset UART7
     1: resets UART7

Bit 29 DACRST: DAC reset
     Set and cleared by software.
     0: does not reset the DAC interface
     1: resets the DAC interface

Bit 28 PWRRST: Power interface reset
     Set and cleared by software.
     0: does not reset the power interface
     1: resets the power interface

Bit 27 CECRST: HDMI-CEC reset
     Set and cleared by software.
     0: does not reset HDMI-CEC
     1: resets HDMI-CEC

Bit 26 CAN2RST: CAN2 reset
     Set and cleared by software.
     0: does not reset CAN2
     1: resets CAN2

Bit 25 CAN1RST: CAN1 reset
     Set and cleared by software.
     0: does not reset CAN1
     1: resets CAN1

Bit 24 I2C4RST: I2C4 reset
     Set and cleared by software.
      0: does not reset I2C4
      1: resets I2C4

Bit 23 I2C3RST: I2C3 reset
     Set and cleared by software.
     0: does not reset I2C3
     1: resets I2C3

Bit 22 I2C2RST: I2C2 reset
     Set and cleared by software.
     0: does not reset I2C2
     1: resets I2C2

Bit 21 I2C1RST: I2C1 reset
     Set and cleared by software.
     0: does not reset I2C1
     1: resets I2C1

Bit 20 UART5RST: UART5 reset
     Set and cleared by software.
     0: does not reset UART5
     1: resets UART5

Bit 19 UART4RST: USART4 reset
     Set and cleared by software.
     0: does not reset UART4
     1: resets UART4

Bit 18 USART3RST: USART3 reset
     Set and cleared by software.
     0: does not reset USART3
     1: resets USART3

Bit 17 USART2RST: USART2 reset
     Set and cleared by software.
     0: does not reset USART2
     1: resets USART2

Bit 16 SPDIFRXRST: SPDIFRX reset
     Set and cleared by software.
     0: does not reset SPDIFRX
     1: resets SPDIFRX

Bit 15 SPI3RST: SPI3 reset
     Set and cleared by software.
     0: does not reset SPI3
     1: resets SPI3

Bit 14 SPI2RST: SPI2 reset
     Set and cleared by software.
     0: does not reset SPI2
     1: resets SPI2

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGRST: Window watchdog reset
     Set and cleared by software.
     0: does not reset the window watchdog
     1: resets the window watchdog

Bit 10 Reserved, must be kept at reset value.

Bit 9 LPTIM1RST: Low-power timer 1 reset
     Set and cleared by software.
     0: does not reset LPTMI1
     1: resets LPTMI1

Bit 8 TIM14RST: TIM14 reset
     Set and cleared by software.
     0: does not reset TIM14
     1: resets TIM14

Bit 7 TIM13RST: TIM13 reset
     Set and cleared by software.
     0: does not reset TIM13
     1: resets TIM13

Bit 6 TIM12RST: TIM12 reset
     Set and cleared by software.
     0: does not reset TIM12
     1: resets TIM12

Bit 5 TIM7RST: TIM7 reset
     Set and cleared by software.
     0: does not reset TIM7
     1: resets TIM7

Bit 4 TIM6RST: TIM6 reset
     Set and cleared by software.
     0: does not reset TIM6
     1: resets TIM6

Bit 3 TIM5RST: TIM5 reset
     Set and cleared by software.
     0: does not reset TIM5
     1: resets TIM5

Bit 2 TIM4RST: TIM4 reset
     Set and cleared by software.
     0: does not reset TIM4
     1: resets TIM4

Bit 1 TIM3RST: TIM3 reset
     Set and cleared by software.
     0: does not reset TIM3
     1: resets TIM3

Bit 0 TIM2RST: TIM2 reset
     Set and cleared by software.
     0: does not reset TIM2
     1: resets TIM2

*

Offline tha

  • *****
  • 4663
    • View Profile
Re: STM32F7 5 Reset and clock control (RCC)
« Reply #39 on: September 23, 2022, 02:57:23 pm »
5.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.



Bits 31:27 Reserved, must be kept at reset value.

Bit 26 LTDCRST: LTDC reset
    This bit is set and reset by software.
    0: does not reset LCD-TFT
    1: resets LCD-TFT

Bits 27:24 Reserved, must be kept at reset value.

Bit 23 SAI2RST: SAI2 reset
     This bit is set and cleared by software.
     0: does not reset SAI2
     1: resets SAI2

Bit 22 SAI1RST: SAI1 reset
     This bit is set and reset by software.
     0: does not reset SAI1
     1: resets SAI1

Bit 21 SPI6RST: SPI6 reset
     This bit is set and cleared by software.
     0: does not reset SPI6
     1: resets SPI6

Bit 20 SPI5RST: SPI5 reset
     This bit is set and cleared by software.
     0: does not reset SPI5
     1: resets SPI5

Bit 19 Reserved, must be kept at reset value.

Bit 18 TIM11RST: TIM11 reset
     This bit is set and cleared by software.
     0: does not reset TIM11
     1: resets TIM14

Bit 17 TIM10RST: TIM10 reset
     This bit is set and cleared by software.
     0: does not reset TIM10
     1: resets TIM10

Bit 16 TIM9RST: TIM9 reset
     This bit is set and cleared by software.
     0: does not reset TIM9
     1: resets TIM9

Bit 15 Reserved, must be kept at reset value.

Bit 14 SYSCFGRST: System configuration controller reset
     This bit is set and cleared by software.
     0: does not reset the System configuration controller
     1: resets the System configuration controller

Bit 13 SPI4RST: SPI4 reset
     This bit is set and cleared by software.
     0: does not reset SPI4
     1: resets SPI4

Bit 12 SPI1RST: SPI1 reset
     This bit is set and cleared by software.
     0: does not reset SPI1
     1: resets SPI1

Bit 11 SDMMC1RST: SDMMC1 reset
     This bit is set and cleared by software.
     0: does not reset the SDMMC1 module
     1: resets the SDMMC1 module

Bits 10:9 Reserved, must be kept at reset value.

Bit 8 ADCRST: ADC interface reset (common to all ADCs)
     This bit is set and cleared by software.
     0: does not reset the ADC interface
     1: resets the ADC interface

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 USART6RST: USART6 reset
     This bit is set and cleared by software.
     0: does not reset USART6
     1: resets USART6

Bit 4 USART1RST: USART1 reset
     This bit is set and cleared by software.
     0: does not reset USART1
     1: resets USART1

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 TIM8RST: TIM8 reset
     This bit is set and cleared by software.
     0: does not reset TIM8
     1: resets TIM8

Bit 0 TIM1RST: TIM1 reset
     This bit is set and cleared by software.
     0: does not reset TIM1
     1: resets TIM1