STM32F7 5 Reset and clock control (RCC)

5.3.10 RCC AHB1 peripheral clock register (RCC_AHB1ENR)

Address offset: 0x30
Reset value: 0x0010 0000
Access: no wait state, word, half-word and byte access.



Bit 31 Reserved, must be kept at reset value.

Bit 30 OTGHSULPIEN: USB OTG HSULPI clock enable
     บิตนี้ถูกเซ็ตและเคลียร์โดย software.
     0: USB OTG HS ULPI clock ถูกปิดใช้งาน
     1: USB OTG HS ULPI clock ถูกเปิดใช้งาน

Bit 29 OTGHSEN: USB OTG HS clock enable
     This bit is set and cleared by software.
     0: USB OTG HS clock disabled
     1: USB OTG HS clock enabled

Bit 28 ETHMACPTPEN: Ethernet PTP clock enable
     This bit is set and cleared by software.
     0: Ethernet PTP clock disabled
     1: Ethernet PTP clock enabled

Bit 27 ETHMACRXEN: Ethernet Reception clock enable
     This bit is set and cleared by software.
     0: Ethernet Reception clock disabled
     1: Ethernet Reception clock enabled

Bit 26 ETHMACTXEN: Ethernet Transmission clock enable
     This bit is set and cleared by software.
     0: Ethernet Transmission clock disabled
     1: Ethernet Transmission clock enabled

Bit 25 ETHMACEN: Ethernet MAC clock enable
     This bit is set and cleared by software.
     0: Ethernet MAC clock disabled
     1: Ethernet MAC clock enabled

Bit 24 Reserved, must be kept at reset value.

Bit 23 DMA2DEN: DMA2D clock enable
     This bit is set and cleared by software.
     0: DMA2D clock disabled
     1: DMA2D clock enabled

Bit 22 DMA2EN: DMA2 clock enable
     This bit is set and cleared by software.
     0: DMA2 clock disabled
     1: DMA2 clock enabled

Bit 21 DMA1EN: DMA1 clock enable
     This bit is set and cleared by software.
     0: DMA1 clock disabled
     1: DMA1 clock enabled

Bit 20 DTCMRAMEN: DTCM data RAM clock enable
     This bit is set and cleared by software.
     0: DTCM RAM clock disabled
     1: DTCM RAM clock enabled

Bit 19 Reserved, must be kept at reset value.

Bit 18 BKPSRAMEN: Backup SRAM interface clock enable
     This bit is set and cleared by software.
     0: Backup SRAM interface clock disabled
     1: Backup SRAM interface clock enabled

Bits 17:13 Reserved, must be kept at reset value.

Bit 12 CRCEN: CRC clock enable
     This bit is set and cleared by software.
     0: CRC clock disabled
     1: CRC clock enabled

Bit 11 Reserved, must be kept at reset value.

Bit 10 GPIOKEN: IO port K clock enable
     This bit is set and cleared by software.
     0: IO port K clock disabled
     1: IO port K clock enabled

Bit 9 GPIOJEN: IO port J clock enable
     This bit is set and cleared by software.
     0: IO port J clock disabled
     1: IO port J clock enabled

Bit 8 GPIOIEN: IO port I clock enable
     This bit is set and cleared by software.
     0: IO port I clock disabled
     1: IO port I clock enabled

Bit 7 GPIOHEN: IO port H clock enable
     This bit is set and cleared by software.
     0: IO port H clock disabled
     1: IO port H clock enabled

Bit 6 GPIOGEN: IO port G clock enable
     This bit is set and cleared by software.
     0: IO port G clock disabled
     1: IO port G clock enabled

Bit 5 GPIOFEN: IO port F clock enable
     This bit is set and cleared by software.
     0: IO port F clock disabled
     1: IO port F clock enabled

Bit 4 GPIOEEN: IO port E clock enable
     This bit is set and cleared by software.
     0: IO port E clock disabled
     1: IO port E clock enabled

Bit 3 GPIODEN: IO port D clock enable
     This bit is set and cleared by software.
     0: IO port D clock disabled
     1: IO port D clock enabled

Bit 2 GPIOCEN: IO port C clock enable
     This bit is set and cleared by software.
     0: IO port C clock disabled
     1: IO port C clock enabled

Bit 1 GPIOBEN: IO port B clock enable
     This bit is set and cleared by software.
     0: IO port B clock disabled
     1: IO port B clock enabled

Bit 0 GPIOAEN: IO port A clock enable
     This bit is set and cleared by software.
     0: IO port A clock disabled
     1: IO port A clock enabled