8.5 DMA registersThe DMA registers ต้องถูกเข้าถึงโดย words (32 bits).
8.5.1 DMA low interrupt status register (DMA_LISR)Address offset: 0x00
Reset value: 0x0000 0000

Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5
TCIF[3:0]: stream x transfer complete interrupt flag (x = 3..0)
บิตนี้ถูกเซ็ตโดย hardware. มันถูกเคลียร์โดย software โดยเขียน 1 ไปยังบิตที่ตรงกันใน the
DMA_LIFCR register.
0: ไม่มี transfer complete event บน stream x
1: a transfer complete event เกิดขึ้นบน stream x
Bits 26, 20, 10, 4
HTIF[3:0]: stream x half transfer interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no half transfer event on stream x
1: a half transfer event occurred on stream x
Bits 25, 19, 9, 3
TEIF[3:0]: stream x transfer error interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no transfer error on stream x
1: a transfer error occurred on stream x
Bits 24, 18, 8, 2
DMEIF[3:0]: stream x direct mode error interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No direct mode error on stream x
1: a direct mode error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0
FEIF[3:0]: stream x FIFO error interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no FIFO error event on stream x
1: a FIFO error event occurred on stream x